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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8580 데이터시트(PDF) 53 Page - Wolfson Microelectronics plc |
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WM8580 데이터시트(HTML) 53 Page - Wolfson Microelectronics plc |
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53 / 97 page  Production Data WM8580 w PD Rev 4.3 August 2007 53 OSC CLK (MHz) PRE- SCALE _x F1 (MHz) F2 (MHz) R PLLx_N (Hex) PLLx_K (Hex) FREQ MODE_x [1:0] POST- SCALE_x PLLxCLK (MHz) 12 0 12 98.304 8.192 8 C49BA 00 1 24.576 12 0 12 98.304 8.192 8 C49BA 01 0 24.576 12 0 12 98.304 8.192 8 C49BA 01 1 12.288 12 0 12 98.304 8.192 8 C49BA 10 0 12.288 12 0 12 98.304 8.192 8 C49BA 10 1 6.144 12 0 12 98.304 8.192 8 C49BA 11 0 8.192 12 0 12 98.304 8.192 8 C49BA 11 1 4.096 24 1 12 90.3168 7.5264 7 21B089 00 1 22.5792 24 1 12 90.3168 7.5264 7 21B089 01 0 22.5792 24 1 12 90.3168 7.5264 7 21B089 01 1 11.2896 24 1 12 90.3168 7.5264 7 21B089 10 0 11.2896 24 1 12 90.3168 7.5264 7 21B089 10 1 5.6448 24 1 12 90.3168 7.5264 7 21B089 11 0 7.5264 24 1 12 90.3168 7.5264 7 21B089 11 1 3.7632 27 1 13.5 98.304 7.2818 7 1208A5 00 1 24.576 27 1 13.5 98.304 7.2818 7 1208A5 01 1 12.288 27 1 13.5 90.3168 6.6901 6 2C2B24 00 1 22.5792 27 1 13.5 90.3168 6.6901 6 2C2B24 01 1 11.2896 Table 46 User Mode PLL Configuration Examples When considering settings not shown in this table, the key configuration parameters which must be selected for optimum operation are: • 90MHz ≤ f2 ≤ 100MHz • 5 ≤ PLLx_N ≤ 13 • OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz CLOCK OUTPUT (CLKOUT) AND MCLK OUTPUT (MCLK) The clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be used as a clock source pin for providing the central clock reference for an audio system. The CLKOUT clock source can be selected from OSCCLK, PLLACLK or PLLBCLK. The control bits for the CLKOUT signal are shown in Table 47. The MCLK pin can be configured as an input or output – the WM8580 should be powered down when switching MCLK between an input and an output. As an output, MCLK can be sourced from OSCCLK, PLLACLK or PLLBCLK. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6:5 MCLKOUTSRC 00 MCLK pin output source 00 = Input – Source MCLK pin 01 = Output – Source PLLACLK 10 = Output – Source PLLBCLK 11 = Output – Source OSCCLK R7 PLLB 4 07h 8:7 CLKOUTSRC 11 CLKOUT pin source 00 = No Output (tristate) 01 = Output – Source PLLACLK 10 = Output – Source PLLBCLK 11 = Output – Source OSCCLK Table 47 MCLK and CLKOUT Control |
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