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WM8580 데이터시트(PDF) 12 Page - Wolfson Microelectronics plc

부품명 WM8580
상세설명  Multichannel CODEC with S/PDIF Transceiver
PDF  97 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8580 데이터시트(HTML) 12 Page - Wolfson Microelectronics plc

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WM8580
Production Data
w
PD Rev 4.3 August 2007
12
TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD (dB) - THD is a ratio, of the rms values, of Distortion/Signal.
4.
Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5.
Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6.
Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
MASTER CLOCK TIMING
ADCMCLK/
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25
oC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
ADCMCLK and MCLK System clock
pulse width high
tMCLKH
11
ns
ADCMCLK and MCLK System clock
pulse width low
tMCLKL
11
ns
ADCMCLK and MCLK System clock
cycle time
tMCLKY
28
ns
ADCMCLK and MCLK Duty cycle
40:60
60:40
Table 3 Master Clock Timing Requirements



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