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SN74ACT596 데이터시트(PDF) 17 Page - Texas Instruments |
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SN74ACT596 데이터시트(HTML) 17 Page - Texas Instruments |
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17 / 31 page ![]() – 8mil to 12mil trace width – Lengths less than 12cm to minimize transmission line effects – Avoid 90° corners for signal traces – Use an unbroken ground plane below signal traces – Flood fill areas around signal traces with ground – For traces longer than 12cm • Use impedance controlled traces • Source-terminate using a series damping resistor near the output • Avoid branches; buffer signals that must branch separately 8.4.2 Layout Example W W ≥ 5W WORST BETTER BEST Figure 8-3. Example Trace Corners for Improved Signal Integrity 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND V CC GND V CC 0.1 F Figure 8-4. Example Bypass Capacitor Placement for TSSOP and Similar Packages 0.1 F VCC GND 1 20 10 11 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 GND V CC GND Figure 8-5. Example Bypass Capacitor Placement for WQFN and Similar Packages 1 2 3 6 5 4 GND GND V CC 0.1 F V CC Figure 8-6. Example Bypass Capacitor Placement for SOT, SC70 and Similar Packages www.ti.com SN74ACT596-Q1 SCASE34 – NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74ACT596-Q1 |
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