being damaged. It is important for the output power of the device to be limited to avoid damage due to

overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all

times.

When placed into the high-impedance state, the output will neither source nor sink current, with the exception of

minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output

voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to

the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected

to the output to provide a known voltage at the output while it is in the high-impedance state. The value of

the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations.

Typically, a 10kΩ resistor can be used to meet these requirements.

Unused open-drain CMOS outputs should be left disconnected.

7.3.3 TTL-Compatible CMOS Inputs

This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL

logic devices by having a reduced input voltage threshold.

TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with

the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the

maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given

in the Electrical Characteristics, using Ohm's law (R = V ÷ I).

TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined

by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this

specification will result in excessive power consumption and could cause oscillations. More details can be found

in the Implications of Slow or Floating CMOS Inputs application report.

Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be

terminated at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down

resistor can be added to provide a valid input voltage during these times. The resistor value will depend on

multiple factors; however, a 10kΩ resistor is recommended and typically will meet all requirements.

7.3.4 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the

data sheet where packages include this feature.

Package

We able Flank Lead

PCB

Pad

Standard Lead

Package

Solder

Figure 7-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After

Soldering

Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with

automatic optical inspection (AOI). As shown in Figure 7-2, a wettable flank can be dimpled or step-cut to

provide additional surface area for solder adhesion which assists in reliably creating a side fillet. See the

mechanical drawing for additional details.

SN74ACT596-Q1

SCASE34 – NOVEMBER 2024

www.ti.com

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