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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS41 데이터시트(PDF) 139 Page - Toshiba Semiconductor |
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TMP93CS41 데이터시트(HTML) 139 Page - Toshiba Semiconductor |
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139 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-137 7 6 5 4 3 2 1 0 Bit symbol CAP3IN CAP34M1 CAP34M0 CLE T5CLK1 T5CLK0 Read/Write W R/W R/W R/W After reset 1 0 0 0 0 0 Function 0: Software capture 1: Don’t care Capture timing 00: Disable INT6 occurs at rising edge. 01: TI6 ↑ TI7 ↑ INT6 occurs at rising edge. 10: TI6 ↑ TI6 ↓ INT6 occurs at falling edge. 11: TFF1 ↑ TFF1 ↓ INT6 occurs at rising edge. 1: UC5 clear enable Timer 5 source clock 00: TI6 01: φT1 10: φT4 11: φT16 Figure 3.9.7 16-Bit Timer Control Register (T5MOD) (2/2) Capture control INT6 Control 00 Capture disable 01 CAP3 at TI6 rise CAP4 at TI7 rise Interrupt occurs at the rising edge of TI6 (INT6) input. 10 CAP3 at TI6 rise CAP4 at TI6 fall Interrupt occurs at the falling edge of TI6 (INT6) input. 11 CAP3 at TFF1 rise CAP4 at TFF1 fall Interrupt occurs at the rising edge of TI6 (INT6) input. Timer 5 capture timing 0 The up counter 5 value is loaded to CAP3 1 Always read as “1” Software capture T5MOD (0048H) |
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