TMP93CS44 datasheet(124/224 Pages) TOSHIBA

124 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-122

The serial channel has a buffer register for transmitting and receiving operations, in order to

temporarily store transmitted or received data, so that transmitting and receiving operations

can be done independently (Full duplex).

However, in I/O interface mode, SCLK (Serial clock) pin is used for both transmission and

receiving, the channel becomes half duplex.

The receiving data register is of a double buffer structure to prevent the occurrence of overrun

error and provides one frame of margin before CPU reads the received data. The receiving data

By using CTS and RTS (there is no RTS pin, so any 1 port must be controlled by software), it

is possible to halt data send until the CPU finishes reading receive data every time a frame is

received (Handshake function).

In the UART mode, a check function is added not to start the receiving operation by error

start bits due to noise. The channel starts receiving data only when the start bit is detected to

be normal at least twice in three samplings.

When the transmission buffer becomes empty and requests the CPU to send the next

transmission data, or when data is stored in the receiving data register and the CPU is

requested to read the data, INTTX or INTRX interrupt occurs. Besides, if an overrun error,

parity error, or framing error occurs during receiving operation, flag SC0CR/SC1CR<OERR,

PERR, FERR> will be set.

The serial channel 0/1 includes a special baud rate generator, which can set any baud rate by

dividing the frequency of 4 clocks (

φT0, φT2, φT8, and φT32) from the internal prescaler (shared

by 8- or 16-bit timer) by the value 1 to 16. In addition, serial channel 0/1 can operated by using

external input clock (SCLK).

In I/O interface mode, it is possible to input synchronous signals as well as to transmit or

receive data by external clock.

TMP93CS44 데이터시트(PDF) 124 Page - Toshiba Semiconductor