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TMP93CS44 데이터시트(PDF) 176 Page - Toshiba Semiconductor |
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TMP93CS44 데이터시트(HTML) 176 Page - Toshiba Semiconductor |
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176 / 224 page ![]() TMP93CS44/S45 2004-02-10 93CS44-174 3.11 AD Converter TMP93CS44/S45 incorporate a high-speed, high-precision 10-bit analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are also used as input-only port 5 and can be also used as input ports. Figure 3.11.1 Block Diagram of AD Converter Note 1: When the power supply current is reduced in IDLE2, IDLE1, STOP mode, there is possible to set a standby enabling the internal comparator due to a timing. Stop operation of AD converter before execution of “HALT” instruction. Note 2: In regard to the lowest operation frequency. The operation of AD converter is guaranteed with clock of fFPH ≥ 4 MHz (Used fc clock). Is not guaranteed with fs clock. Internal data bus ADMOD0 <EOCF> <ADBF> <ITM0> <REPET> <SCAN> <ADS> ADMOD1 <ADCH2:0> <VREFON> <ADTRGE> AD converter control circuit Scan Repeat Interrupt Busy End Start ADTRG AD conversion result register ADREG04L to 37L ADREG04H to 37H DA converter Sample hold Channel select AN7 (P57) AN6 (P56) AN5 (P55) AN4 (P54) AN3/ ADTRG (P53) AN2 (P52) AN1 (P51) AN0 (P50) VREFH VREFL INTAD interrupt |
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