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TMP86FS28DFG 데이터시트(PDF) 184 Page - Toshiba Semiconductor

부품명 TMP86FS28DFG
상세설명  8 Bit Microcontroller
PDF  272 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86FS28DFG 데이터시트(HTML) 184 Page - Toshiba Semiconductor

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Page 172
13. Asynchronous Serial interface (UART0 )
13.2 Control
TMP86FS28DFG
13.2 Control
UART0 is controlled by the UART0 Control Registers (UART0CR1, UART0CR2). The operating status can be
monitored using the UART status register (UART0SR).
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UART0CR1<RXE> and UART0CR1<TXE> should be set to “0” before UART0CR1<BRG> is changed.
Note: When UART0CR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when
UART0CR2<RXDNC> = “10”, longer than 192/fc [s]; and when UART0CR2<RXDNC> = “11”, longer than 384/fc [s].
UART0 Control Register1
UART0CR1
(0FE5H)
76
543
210
TXE
RXE
STBT
EVEN
PE
BRG
(Initial value: 0000 0000)
TXE
Transfer operation
0:
1:
Disable
Enable
Write
only
RXE
Receive operation
0:
1:
Disable
Enable
STBT
Transmit stop bit length
0:
1:
1 bit
2 bits
EVEN
Even-numbered parity
0:
1:
Odd-numbered parity
Even-numbered parity
PE
Parity addition
0:
1:
No parity
Parity
BRG
Transmit clock select
000:
001:
010:
011:
100:
101:
110:
111:
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC3 ( Input INTTC3)
fc/96
UART0 Control Register2
UART0CR2
(0FE6H)
765
432
1
0
RXDNC
STOPBR
(Initial value: **** *000)
RXDNC
Selection of RXD input noise
rejection time
00:
01:
10:
11:
No noise rejection (Hysteresis input)
Rejects pulses shorter than 31/fc [s] as noise
Rejects pulses shorter than 63/fc [s] as noise
Rejects pulses shorter than 127/fc [s] as noise
Write
only
STOPBR
Receive stop bit length
0:
1:
1 bit
2 bits



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