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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AX88796BLF 데이터시트(PDF) 30 Page - ASIX Electronics Corporation |
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AX88796BLF 데이터시트(HTML) 30 Page - ASIX Electronics Corporation |
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30 / 82 page  ASIX ELECTRONICS CORPORATION 30 AX88796BLF / AX88796BLI 5.0 Registers Operation 5.1 MAC Control and Status Registers (CSR) All registers of MAC Core are 8-bit wide except data port (DP). Data Port is optional 8 or 16-bit wide by WTS (DCR). Offset 01h to 0Fh mapped into pages, which are selected by PS (Page Select) in the Command Register. Offset Page0 Page1 Page2 Page3 00H Command Register (CR) 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H, 11H Data Port (DP) 12H Inter-frame Gap Segment 1 (IFGS1) 13H Inter-frame Gap Segment 2 (IFGS2) 14H MII/EEPROM Access 15H Buffer Type Configure Register (BTCR) 16H Inter-frame Gap (IFG) 17H Device Status Register (DSR) / Back-pressure Jam Limit Count (BJLC) 18H Max Frame Size [7:0] 19H Max Frame Size [11:8] 1AH Flow Control Register (FCR) 1BH MAC Configure Register (MCR) 1CH Current TX End Page Register (CTEPR) / VLAN_ID_0 1DH Reserved / VLAN_ID_1 1EH Reserved / Big-Endian Register (BER) 1FH Software Reset / Host Wake up (HWAKE) |
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