AX88796BLF datasheet(71/82 Pages) ASIX

71 / 82 page

ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

7.4.5 Burst Reads Access Timing

Burst read access is enabled when set FIFO_SEL(SA5) is driven high during a read access. This is normally

accomplished by connecting the FIFO_SEL(SA5) signal to a high-order address line. This mode is useful when

the host processor must increment its address when accessing the AX88796B.

In this mode, performance is improved by allowing an unlimited number of back-to-back WORDS read cycles.

AX88796B base on SA0 or SA1 address toggles to identify WORD access cycle time. Host can set burst cycle

base on SA0 or SA1 toggle by BCB1 (CR page3 Offset 0Dh).

Tdoff

Tdoh

Tadv

Tdv

Tdon

Trdh

Tah

Tas u

Tacyc

Tacy c

Tacyc

FIFO_SEL(SA5)

SA1 or SA0

CSn, RDn

SD[15:0]

Symbol

Description

Min

Typ.

Max

Units

Tasu

ADDRESS SETUP TIME

Tah

ADDRESS HOLD TIME

Tdv

DATA VALID TIME FROM RDn

33*

35*

Tadv

DATA VALID TIME FROM ADDRESS

33*

35*

Tdoh

DATA OUTPUT HOLD TIME

Trdh

RDn HI REQUIRE TIME

Tacyc

READ CYCLE TIME

Tdon

DATA BUFFER TURN ON

Tdoff

DATA BUFFER TURN OFF

1 : Base on SD bus output load 25pF

2 : Base on SD bus output load 50pF

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