AX88796BLF datasheet(42/82 Pages) ASIX

42 / 82 page

ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

5.1.26 Physical Address Register 0 (PAR0)

Page1 Offset 01H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

PAR0

Physical Address Register 0

5.1.27 Physical Address Register 1 (PAR1)

Page1 Offset 02H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

PAR1

Physical Address Register 1

5.1.28 Physical Address Register 2 (PAR2)

Page1 Offset 03H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

PAR2

Physical Address Register 2

5.1.29 Physical Address Register 3 (PAR3)

Page1 Offset 04H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

PAR3

Physical Address Register 3

5.1.30 Physical Address Register 4 (PAR4)

Page1 Offset 05H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

PAR4

Physical Address Register 4

5.1.31 Physical Address Register 5 (PAR5)

Page1 Offset 06H (Read/Write)

Field

Name

Description (Default = 00h)

7:0

PAR5

Physical Address Register 5

The physical address registers are used to compare the destination address of incoming packets for rejecting or

accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the

sequence in PAR0 ~ PAR5 to the bit sequence of the received packet.

AX88796BLF 데이터시트(PDF) 42 Page - ASIX Electronics Corporation

AX88796BLF 데이터시트(HTML) 42 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL