AX88796BLF datasheet(52/82 Pages) ASIX

52 / 82 page

ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

5.1.73 VLAN ID 0 Register (VIDR0)

Offset 1CH (Write)

Field

Name

Description

7:0

VIDR0

VLAN ID [7:0]

5.1.74 Current TX End Page Register (CTEPR)

Offset 1CH (Read)

Field

Name

Description (Default = 00h)

TXCQF

TX Command Queue full

When set, indicate the TX Command queue was full. Host must check this status before

queuing next transmit page and byte count.

6:0

CTEPR

AX88796B will update CTEPR (current TX end page)

After every transmitting completed without collision.

It is for Host to conform how many free page can reuse for next transmitting.

The value is from 40h to 7Fh. It will be 00h when reset or STP.

5.1.75 VLAN ID 1 Register (VIDR1)

Offset 1DH (Write)

Field

Name

Description

7:5

PRI

Frame’s priority

CFI

Canonical Address Frame Indicator

3:0

VIDR1

VLAN ID [11:8]

5.1.76 Big-Endian Register (BER)

Offset 1EH (Write)

Field

Name

Description (Default = 00h)

7:0

All zero, (Default): little-endian

If not all zero means set data byte order as big-endian mode.

Note: This mode can be used by 32-bit big-endian mode of processors operating with an

external 16-bit bus only.

5.1.77 Host Wake Up Register (HWUR)

Offset 1FH (Write)

Field

Name

Description

7:1

Reserved

HWAKE

(SC)

Host write one to wake up AX88796B from D2 power saving. It will be auto clear when

wake up.

5.1.78 Software Reset

Offset 1FH (Read)

Field

Name

Description

7:0

Don’t care this read value.

AX88796BLF 데이터시트(PDF) 52 Page - ASIX Electronics Corporation

AX88796BLF 데이터시트(HTML) 52 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL