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DSP56721 데이터시트(PDF) 27 Page - Freescale Semiconductor, Inc

부품명 DSP56721
상세설명  SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
PDF  54 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56721 데이터시트(HTML) 27 Page - Freescale Semiconductor, Inc

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
27
2.2.4
Enhanced Serial Audio Interface (ESAI) Timing
See Table 13 For ESAI timing parameters and Figure 20, Figure 21, Figure 22, and Figure 23 for timing diagrams.
Table 13. Enhanced Serial Audio Interface Timing Parameters
No.
Characteristics1, 3, 4
Symbol
Expression5
Min
Max
Condition2 Unit
62
Clock cycle5
tSSICC
4
× T
c
4
× Tc
20.0
20.0
–
–
i ck
i ck
ns
63
Clock high period
• For internal clock
–
2
× T
c
10
–
–
ns
• For external clock
2
× Tc
10
–
–
64
Clock low period
• For internal clock
–
2
× T
c
10
–
–
ns
• For external clock
2
× Tc
10
–
–
65
SCKR rising edge to FSR out (bl) high
–
–
–
–
17.0
7.0
x ck
i ck a
ns
66
SCKR rising edge to FSR out (bl) low
–
–
–
–
17.0
7.0
x ck
i ck a
ns
67
SCKR rising edge to FSR out (wr) high6
––
–
–
19.0
9.0
x ck
i ck a
ns
68
SCKR rising edge to FSR out (wr) low6
––
–
–
19.0
9.0
x ck
i ck a
ns
69
SCKR rising edge to FSR out (wl) high
–
–
–
–
16.0
6.0
x ck
i ck a
ns
70
SCKR rising edge to FSR out (wl) low
–
–
–
–
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
––
12.0
19.0
–
–
x ck
i ck
ns
72
Data in hold time after SCKR falling edge
–
–
3.5
9.0
–
–
x ck
i ck
ns
73
FSR input (bl, wr) high before SCKR falling edge 6
––
2.0
12.0
–
–
x ck
i ck a
ns
74
FSR input (wl) high before SCKR falling edge
–
–
2.0
12.0
–
–
x ck
i ck a
ns
75
FSR input hold time after SCKR falling edge
–
–
2.5
8.5
–
–
x ck
i ck a
ns
76
Flags input setup before SCKR falling edge
–
–
0.0
19.0
–
–
x ck
i ck s
ns
77
Flags input hold time after SCKR falling edge
–
–
6.0
0.0
–
–
x ck
i ck s
ns
78
SCKT rising edge to FST out (bl) high
–
–
–
–
18.0
8.0
x ck
i ck
ns
79
SCKT rising edge to FST out (bl) low
–
–
–
–
20.0
10.0
x ck
i ck
ns



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