DSP56721 datasheet(45/54 Pages) FREESCALE

부품명	DSP56721

상세설명	SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors

PDF	54 Pages

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제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Table 21. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

Tclk

–

Input setup to LCLK (except LGTA/LUPWAIT)

Tin_s

–

Input hold from LCLK (except LGTA/LUPWAIT)1

Tin_h

-1

–

LGTA valid time

Tgta

–

LUPWAIT valid time

Tupwait

–

LALE negedge to LAD (address phase) invalid (address latch hold time)

Tale_h

–

LALE valid time

Tale

–

Output setup from LCLK (except LAD[23:0] and LALE)

Tout_s

–

Output hold from LCLK (except LAD[23:0] and LALE)

Tout_h

–

LAD[23:0] output setup from LCLK

Tad_s

–

LAD[23:0] output hold from LCLK

Tad_h

–

LCLK to output high impedance for LAD[23:0]

Tad_z

–

9ns

Notes:

1. A negative hold time means that the signal could be invalid before the LCLK rising edge.

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