Freescale Semiconductor

37

339

Delay from write data strobe deassertion to

host request assertion for “Last Data Register” write

4, 7, 9

2

× T

C

10.0

–

ns

340

Delay from data strobe assertion to

host request deassertion for “Last Data Register” read or write (HROD =

0)

4, 8, 9

––

19.1

ns

341

Delay from data strobe assertion to

host request deassertion for “Last Data Register” read or write (HROD =

1, open drain Host Request)

4, 8, 9, 10

–

–

300.0

ns

342

Delay from DMA HACK deassertion to HOREQ assertion

ns

• For “Last Data Register” read

4

2

× T

29.1

–

• For “Last Data Register” write

4

1

× T

24.1

–

• For other cases

–

0.0

–

343

Delay from DMA HACK assertion to HOREQ deassertion

•HROD = 0

4

––

20.2

ns

344

Delay from DMA HACK assertion to HOREQ deassertion for “Last Data

Register” read or write

• HROD = 1, open drain Host Request

4, 10

–

–

300.0

ns

Notes:

1.

In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.

2.

3.

The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

4.

The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.

5.

This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without

first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.

6.

This timing is applicable only if two consecutive reads from one of these registers are executed.

7.

The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

8.

The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data

strobe mode.

9.

The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.

10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode.

11. HDI24_1 specs match those of HDI24.

Table 18. HDI24 Timing Parameters (Continued)

No.

Characteristics

2

Expression

200 MHz

Unit

Min

Max