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DSP56721 데이터시트(PDF) 18 Page - Freescale Semiconductor, Inc

부품명 DSP56721
상세설명  SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
PDF  54 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56721 데이터시트(HTML) 18 Page - Freescale Semiconductor, Inc

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
18
2.2.1
Serial Host Interface (SHI) SPI Protocol Timing
See Table 11 for SHI SPI protocol timing parameters and Figure 15, Figure 16, Figure 17, and Figure 18 for timing diagrams.
Table 11. Serial Host Interface SPI Protocol Timing Parameters
No.
Characteristics1,3,4
Mode
Filter Mode
Expression
Min
Max
Unit
23
Minimum serial clock cycle = tSPICC(min)
Master/Slave
Bypassed
10 x TC + 9
59.0
–
ns
Very Narrow
10 x TC + 9
59.0
–
ns
Narrow
10 x TC + 133
183.0
–
ns
Wide
10 x TC + 333
373.0
–
ns
XX
Tolerable Spike width on data or clock in
–
Bypassed
–
–
0
ns
Very Narrow
–
–
10
ns
Narrow
–
–
50
ns
Wide
–
–
100
ns
24
Serial clock high period
Master
Bypassed
0.5 x (tSPICC -10)
33.0
–
ns
Very Narrow
0.5 x (tSPICC -10)
33.0
–
ns
Narrow
0.5 x (tSPICC -10)
86.0
–
ns
Wide
0.5 x (tSPICC -10)
121.5
–
ns
Slave
Bypassed
2.5 x TC + 12
22.5
–
ns
Very Narrow
2.5 x TC + 12
22.5
–
ns
Narrow
2.5 x TC + 102
114.5
–
ns
Wide
2.5 x TC + 189
201.5
–
ns
25
Serial clock low period
Master
Bypassed
0.5 x (tSPICC -10)
33.0
–
ns
Very Narrow
0.5 x (tSPICC -10)
33.0
–
ns
Narrow
0.5 x (tSPICC -10)
86.0
–
ns
Wide
0.5 x (tSPICC -10)
121.5
–
ns
Slave
Bypassed
2.5 x TC + 12
22.5
–
ns
Very Narrow
2.5 x TC + 12
22.5
–
ns
Narrow
2.5 x TC + 102
114.5
–
ns
Wide
2.5 x TC + 189
201.5
–
ns
26
Serial clock rise/fall time
Master
Slave
–
–
–
–
–
–
–
5
ns
ns



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