LM98640CVAL datasheet(40/55 Pages) TI2

40 / 55 page

LM98640QML-SP

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

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Table 6. Register Definitions - Analog Configuration (continued)

ADDRESS

(BINARY)

TITLE

BASELINE

(BINARY)

BIT(s)

DESCRIPTION

00 0011

ADC Power Trimming

0101 1011

[7:0]

ADC Power Trimming Register.

[7:6]

Reserved. Set to 2'b01.

[5:3]

ADC Current Trimming 2(Not Binary Weighted)

000 25% Power

001 50% Power

011 75% Power (Default)

111 100% Power

[2:0]

ADC Current Trimming 1 (Not Binary Weighted)

000 25% Power

001 50% Power

011 75% Power (Default)

111 100% Power

00 0100

VCLP Control

0111 0100

[7:0]

Voltage Clamp Buffer Control Register.

[7]

Not Used

[6]

Buffer Enable

0 Disabled. Resistor Ladder is driving VCLP pin.

1 Enabled. Resistor Ladder is buffered to VCLP pin.

[5]

VCLP Enable

0 Disabled. VCLP pin can be externally driven.

1 Enabled. VCLP pin is in output mode.

[4:0]

Voltage Level of VCLP pin.

VCLP range is 200mV to 3.1V in 100mV steps for (binary) settings

00000 to 11101. Settings 11110 and 11111 are not used.

00 0101

LVDS Output Modes

0000 1110

[7:0]

LVDS Output Configuration Register.

[7]

Serializer Data Reset. (Not self-clearing)

[6:4]

Not Used.

[3]

LVDS Output Mode

0 Dual Lane Mode (see Output Mode 1 - Dual Lane)

1 Quad Lane Mode (see Output Mode 2 - Quad Lane)

[2]

LVDS Driver Enable.

0 LVDS Drivers Disabled

1 LVDS Drivers Enabled

(Note: In Dual Lane Mode TX0 and TX3 are disabled regardless of

driver enable)

[1:0]

LVDS Amplitude and Common Mode Voltage.

00 250mV (1.2V DC Offset)

01 300mV (1.2V DC Offset)

10 350mV (1.1V DC Offset)

11 400mV (1.1V DC Offset)

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