LM98640CVAL datasheet(41/55 Pages) TI2

부품명	LM98640CVAL

상세설명	LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output

PDF	55 Pages

Scroll/Zoom	100%

제조업체	TI2 [Texas Instruments]

홈페이지	https://www.ti.com

Logo

41 / 55 page

LM98640QML-SP

www.ti.com

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

Product Folder Links: LM98640QML-SP

Submit Documentation Feedback

Table 6. Register Definitions - Analog Configuration (continued)

ADDRESS

(BINARY)

TITLE

BASELINE

(BINARY)

BIT(s)

DESCRIPTION

00 0110

Sample & Hold

1000 0001

[7:0]

Sample & Hold Mode Register

[7]

Sample & Hold Mode Enable

0 Disabled.

1 Enabled.

[6:3]

Not Used.

[2:1]

Reference Buffer Power Level

11 100% Power. Used for FINCLK = 20-40MHz.

10 60% Power. Used for FINCLK = 10-20MHz.

01 60% Power. Used for FINCLK = 10-20MHz.

00 30% Power. Used for FINCLK = 5-10MHz.

[0]

Reserved.

00 0111

Status

0000 0000

[7:0]

Status Register. (Read Only)

[7:1]

Not Used.

[0]

False Lock Detect.

Indicates if DLL is locked into a half frequency state.

00 1001

Clock Monitor

0000 0000

[7:0]

Internal Clock Signal Monitor Register

[7:5]

Not Used.

[4:3]

Enable and select clocks to be monitored on the Digital Timing

Monitor. (DTM)

00 Disable Digital Timing Monitor Pins (DTM0, DTM1)

01 Send CLAMPEVEN to DTM0 pin, and SAMPLEEVEN to DTM1

10 Send CLAMPODD to DTM0 pin, and SAMPLEODD to DTM1

11 Send ODD tag and ADC Clock to the DTM.

[2:0]

Reserved. Set to 000.

LM98640CVAL 데이터시트(PDF) 41 Page - Texas Instruments

LM98640CVAL 데이터시트(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

데이터시트 다운로드

링크 URL