| 전자부품 데이터시트 검색엔진 |
|
LAN9252/ML 데이터시트(PDF) 260 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
LAN9252/ML 데이터시트(HTML) 260 Page - Microchip Technology |
|
260 / 329 page ![]() LAN9252 DS00001909A-page 260 2015 Microchip Technology Inc. 12.14.47 EEPROM CONFIGURATION REGISTER Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Offset: 0500h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:2 RESERVED Write 0. RO RO 000000b 1 Force ECAT Access 0: Do not change 1: Reset R/W RO 0b 0 PDI EEPROM Control 0: No 1: Yes (PDI has EEPROM control) R/W RO 0b |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |