LAN9252SLASHML datasheet(264/329 Pages) MICROCHIP

264 / 329 page

LAN9252

DS00001909A-page 264

 2015 Microchip Technology Inc.

12.14.52 MII MANAGEMENT CONTROL/STATUS REGISTER

Note 25:

Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally

blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1)

Offset:

0510h-0511h

Size:

16 bits

Bits

Description

ECAT

Type

PDI

Type

Default

Busy

MI control state machine is idle

MI control state machine is active

Command Error

Last command was successful

Invalid command or write command without write enable

Note:

Cleared with a valid command or by writing “00” to

Command Register.

Read Error

No read error

Read error occurred (PHY or register bi available)

Note:

Cleared by writing this register.

R/W

Note 25

R/W

Note 25

12:10

RESERVED

9:8

Command Register

Write: Initiate command.

Read: Currently executed command

See Note 26.

Commands:

00:

No command / MI Idle (clear error bits)

01:

Read

10:

Write

11:

RESERVED (do not issue)

R/W

Note 25

R/W

Note 25

00b

7:3

PHY Address Offset

00000b

MI Link Detection

(Link configuration, link detection, registers PHY Port Status

Registers)

Not available

MI Link Detection Active

Note 27

Management Interface Control

ECAT control only

MPDI control possible (MII Management ECAT Access State

Write Enable

Write Disabled

Write Enabled

Note:

This bit is always 1 if PDI has MI control. (See

Note 28)

R/W

Note 25

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