LAN9252SLASHML datasheet(280/329 Pages) MICROCHIP

280 / 329 page

LAN9252

DS00001909A-page 280

 2015 Microchip Technology Inc.

12.14.69 SPEED COUNTER START REGISTER

Note:

For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the

highest address.

12.14.70 SPEED COUNTER DIFF REGISTER

Note:

The clock deviation after System Time Difference has settled at a low value can be calculated as follows:

Deviation = Speed Counter Diff / 5(Speed Counter Start + Speed Counter Diff + 2)(Speed Counter Start -

Speed Counter Diff + 2)

Note:

For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the

highest address.

Offset:

0930h-0931h

Size:

16 bits

Bits

Description

ECAT

Type

PDI

Type

Default

RESERVED

Write as 0.

14:0

Bandwidth for adjustment of local copy of System Time (larger

values -> smaller bandwidth and smoother adjustment). A write

access resets the System Time Difference Register and Speed

Counter Diff Register.

Valid range: 0080h-3FFFh.

R/W

1000h

Offset:

0932h-0933h

Size:

16 bits

Bits

Description

ECAT

Type

PDI

Type

Default

15:0

Representation of the deviation between local clock period and

Reference Clock’s clock period (representation: two’s compli-

ment).

Valid Range: +/-(Speed Counter Start Register-7Fh).

0000h

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