ST10F271Z1T3 datasheet(55/185 Pages) STMICROELECTRONICS

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ST10F271Z1

Interrupt system

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9.2

Exception and error traps list

Table 30 shows all of the possible exceptions or error conditions that can arise during run-

time.

Note:

* - All the class B traps have the same trap number (and vector) and the same lower priority

compare to the class A traps and to the resets.

- Each class A traps has a dedicated trap number (and vector). They are prioritized in the

second priority level.

- The resets have the highest priority level and the same trap number.

- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are

serviced.

ASC1 error

PLL unlock / OWD

PWM1 channel 3...0

Table 29.

X-Interrupt detailed mapping (continued)

XP0INT

XP1INT

XP2INT

XP3INT

Table 30.

Trap priorities

Exception condition

Trap

flag

Trap

vector

Vector

location

Trap

number

Trap*

priority

Reset functions:

Hardware reset

Software reset

Watchdog timer overflow

RESET

00’0000h

00h

III

Class A hardware traps:

Non-maskable interrupt

Stack overflow

Stack underflow

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008h

00’0010h

00’0018h

02h

04h

06h

Class B hardware traps:

Undefined opcode

MAC interruption

Protected instruction fault

Illegal word operand access

Illegal instruction access

Illegal external bus access

UNDOPC

MACTRP

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028h

0Ah

Reserved

[002Ch - 003Ch]

[0Bh - 0Fh]

Software traps

TRAP instruction

Any

0000h – 01FCh

in steps of 4h

Any

[00h - 7Fh]

Current

CPU

Priority

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