ST10F271Z1T3 datasheet(16/185 Pages) STMICROELECTRONICS

16 / 185 page

Pin data

ST10F271Z1

16/185

P4.0 –P4.7

85-92

I/O

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the corresponding

output driver to high impedance state. The input threshold is selectable (TTL or

CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open

drain drivers.

In case of an external bus configuration, Port 4 can be used to output the

segment address lines:

P4.0

A16

Segment address line

P4.1

A17

Segment address line

P4.2

A18

Segment address line

P4.3

A19

Segment address line

P4.4

A20

Segment address line

CAN2_RxD

CAN2: receive data input

I/O

SCL

I2C Interface: serial clock

P4.5

A21

Segment address line

CAN1_RxD

CAN1: receive data input

CAN2_RxD

CAN2: receive data input

P4.6

A22

Segment address line

CAN1_TxD

CAN1: transmit data output

CAN2_TxD

CAN2: transmit data output

P4.7

A23

Most significant segment address line

CAN2_TxD

CAN2: transmit data output

I/O

SDA

I2C Interface: serial data

External memory read strobe. RD is activated for every external instruction or

data read access.

WR/WRL

External memory write strobe. In WR-mode this pin is activated for every external

data write access. In WRL mode this pin is activated for low byte data write

accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See

WRCFG in the SYSCON register for mode selection.

READY/

READY

Ready input. The active level is programmable. When the ready function is

enabled, the selected inactive level at this pin, during an external memory

access, will force the insertion of waitstate cycles until the pin returns to the

selected active level.

ALE

Address latch enable output. In case of use of external addressing or of

multiplexed mode, this signal is the latch command of the address lines.

Table 1.

Pin description (continued)

Symbol

Type

Function

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