ST10F271Z1T3 datasheet(56/185 Pages) STMICROELECTRONICS

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Capture / compare (CAPCOM) units

ST10F271Z1

56/185

Capture / compare (CAPCOM) units

The ST10F271Z1 has two 16-channel CAPCOM units which support generation and control

of timing sequences on up to 32 channels with a maximum resolution of 125 ns at 64 MHz

CPU clock.

The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and

waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion,

software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases

for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal

system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows precise

adjustments to application specific requirements. In addition, external count inputs for

CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers

relative to external events.

Each of the two capture/compare register arrays contain 16 dual purpose capture/compare

registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7

or T8, respectively), and programmed for capture or compare functions. Each of the 32

registers has one associated port pin which serves as an input pin for triggering the capture

function, or as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents

of the allocated timer will be latched (captured) into the capture/compare register in

response to an external event at the port pin which is associated with this register. In

addition, a specific interrupt request for this capture/compare register is generated.

Either a positive, a negative, or both a positive and a negative external signal transition at

the pin can be selected as the triggering event. The contents of all registers which have

been selected for one of the five compare modes are continuously compared with the

contents of the allocated timers.

When a match occurs between the timer value and the value in a capture / compare

The input frequencies fTx, for the timer input selector Tx, are determined as a function of the

CPU clocks. The timer input frequencies, resolution and periods which result from the

selected prescaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in

the Table 32 and Table 33 respectively.

The numbers for the timer periods are based on a reload value of 0000h. Note that some

numbers may be rounded to 3 significant figures.

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