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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADC3441 데이터시트(PDF) 3 Page - Texas Instruments |
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ADC3441 데이터시트(HTML) 3 Page - Texas Instruments |
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3 / 88 page  3 ADC3441, ADC3442, ADC3443, ADC3444 www.ti.com SBAS670B – JULY 2014 – REVISED APRIL 2017 Product Folder Links: ADC3441 ADC3442 ADC3443 ADC3444 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Revision History (continued) • Changed specifications of Digital Outputs (LVDS Interface), VOCM parameter in Digital Characteristics table.................... 17 • Changed rising to falling in description of SYSREF reference time parameter in Timing Requirements: General table ... 17 • Changed Typical Characteristics sections: added dither on to all section condition statements, changed Non 23 to excluding HD2, HD3 ............................................................................................................................................................. 19 • Added INL and DNL plots in Typical Characteristics: ADC3441 section ............................................................................. 24 • Changed conditions of Figure 34, Figure 35 ........................................................................................................................ 25 • Added INL and DNL plots in Typical Characteristics: ADC3442 section ............................................................................ 30 • Changed conditions of Figure 67, Figure 68 ........................................................................................................................ 31 • Added INL and DNL plots in Typical Characteristics: ADC3443 section ............................................................................ 36 • Changed conditions of Figure 100, Figure 101 .................................................................................................................... 37 • Added INL and DNL plots in Typical Characteristics: ADC3444 section. ........................................................................... 42 • Changed conditions of Figure 134 ...................................................................................................................................... 43 • Added Figure 141 to Timing Diagrams section .................................................................................................................... 44 • Added Using the SYSREF Input section .............................................................................................................................. 50 • Changed the description about synchronization of the phase of the divided clock in each device to the common sampling clock in Using the SYSREF Input section. ........................................................................................................... 50 • Added ADC3441 Power-Up Requirements section, deleted the Register Initialization section ........................................... 57 • Added last sentence to Detailed Design Procedure section of first typical application........................................................ 75 • Added Chopper On to caption of Figure 198 ...................................................................................................................... 75 • Added Chopper Off to caption of Figure 200 ...................................................................................................................... 76 • Changed the caption of Figure 202 from FFT for 450-MHz Input Signal (Dither On) to FFT for 450-MHz Input Signal (Chopper Off, Dither On) ...................................................................................................................................................... 77 Changes from Original (July 2014) to Revision A Page • Released to production........................................................................................................................................................... 1 |
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