SPSB081 datasheet(15/137 Pages) STMICROELECTRONICS

15 / 137 page

3.3.3

V1_standby mode

The transition from active mode to V1_standby mode is controlled by SPI (STBY_SEL bit and GO_STBY bit in

CR2).

To supply the microcontroller in a low power mode, the V1 voltage regulator remains active.

After the V1_standby command (CSN low to high transition), the device enters V1_standby mode immediately

and the watchdog starts a long open window (tLW). The watchdog is deactivated as soon as the V1 load current

drops below the ICMP threshold (IV1 < ICMP).

The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration, the watchdog is

deactivated upon transition into V1_standby mode without monitoring the V1 load current.

Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting ICMP_CONFIG_EN (Config

Reg) = 1. The ICMP_CONFIG_EN bit is reset to ‘0’ automatically with next SPI command.

LIN and CAN transmitters are switched off in V1_standby mode.

OUT1, OUT2, OUT3, and OUT4 remain in the configuration programmed before the standby command.

V2 voltage regulator remains in the configuration programmed before the standby command. Even though LIN

and CAN transceivers are switched off, they can still wake up the micro (see Table 7).

In V1_standby mode various wake-up sources can be individually programmed. Normally a wake-up event puts

the device into active mode and forces the NINT pin to a low level indicating the wake-up condition to the

microcontroller. Writing IWK (CR 34) = 1 a wake-up event on CAN and wake-up pins forces NINT pin to a low

level indicating the wake-up condition to the microcontroller. However, no change in the SBC mode occurs.

3.3.4

Interrupt

The interrupt signal on NINT pin is generated to communicate a specific event to the microcontroller. NINT is

pulled low after a reaction time when one of the following events occurs.

In active mode, this event can be related to each one of the status flags latched in the global status byte register

(GSBN bit).

A bit register is available to mask each one of these flags:

•

RSTB: MASK_RSTB (0x3F)

•

PLE: MASK_PLE (0x3F)

•

FE: MASK_FE (0x3F)

•

DE: MASK_DE (0x3F)

•

GW: MASK_GW (0x3F)

These masks are common for the generation of GSBN, NINT, and DIAGN (in extended mode).

NINT pulse can also be related to the CAN communication timeout event (no CAN communication for t > tSilence).

The CANTO flag is set. This interrupt can be masked by CANTO_NINT_MASK SPI bit.

In V1 standby mode, it can also be related to the following events:

•

CAN communication timeout (no CAN communication for t > tSILENCE). The CANTO flag is set. This interrupt

can be masked by CANTO_NINT_MASK SPI bit.

•

Wake-up from V1_standby mode by any wake-up source (WU1, WU2, LIN, CAN, TIMER1/2, SPI). This

interrupt can be masked by WU_NINT_MASK SPI bit.

In case of increasing V1 load current during V1_standby mode (IV1 > ICMP), the device remains in standby mode

and the watchdog starts with a long open window. No interrupt signal is generated.

NINT pin is an open drain structure to allow multiple connections.

SPSB081

Operating modes

DS14048 - Rev 3

page 15/137

SPSB081 데이터시트(PDF) 15 Page - STMicroelectronics

SPSB081 데이터시트(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL