SPSB081 datasheet(42/137 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

A 32-bit SPI is used for bidirectional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0 and

CPHA = 0

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed

from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output pins and one

input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If

CSN = 0, the DO-Pin reflects the global error flag (fault condition) of the device.

•

Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is

in high impedance state. A low signal activates the output driver and a serial communication can be started.

The state during CSN = 0 is called a communication frame.

If CSN = low for t > tCSNFAIL, the DO output is switched to high impedance in order not to block the signal

line for other SPI nodes.

•

Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the

rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN

signal the content of the shift register is transferred to data input register. The writing to the selected data

input register is only enabled if exactly 32 bits are transmitted within one communication frame (that is, CSN

low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety

function is implemented to avoid an activation of the output stages by a wrong communication frame.

Note:

Due to this safety functionality, a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI

bus by controlling the CSN signal of the connected IC's is recommended.

•

Serial data out (DO)

The data output driver is activated by a logical low level at the CSN input and it goes from high impedance to

a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input

after a high to low transition of the CSN pin transfers the content of the selected status register into the data

out shift register. Each subsequent falling edge of the CLK shifts the next bit out.

•

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled

at the rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK signal. The

SPI can be driven with a CLK frequency up to 10 MHz.

4.1

ST-SPI

The ST-SPI is a standard used in ST automotive ASSP devices.

This chapter describes the SPI protocol standardization. It defines a common structure of the communication

frames and defines specific addresses for product and status information.

The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to

adapt it to the individual functionality of a particular product. In addition, fail-safe mechanisms are implemented to

protect the communication from external influences and wrong or unwanted usage.

The device serial peripheral interface is compliant to the ST-SPI standard.

SPSB081

Serial peripheral interface (SPI)

DS14048 - Rev 3

page 42/137

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