SPSB081 datasheet(23/137 Pages) STMICROELECTRONICS

23 / 137 page

3.6.1

Change watchdog timing

The watchdog trigger time can be configured by setting the WD_TIME (CR 2) bit. Writing to these bits is

only possible with the first SPI command after setting WD_CONFIG_EN = 1 (Config register (0x3F)). The

WD_CONFIG_EN bit is reset to 0 automatically with next SPI command.

When FAIL_SAFE is active, these SPI registers are not accessible. Therefore, the FAIL_SAFE status needs to be

cleared. In case of a WD_FAIL, the clear is performed by starting a long open window.

When a new configuration has been programmed, the watchdog behaves with the old configuration until the next

trig event.

The new value of WD_TIME is loaded in the watchdog module on the next trig event after the SPI configuration.

The following watchdog cycle uses the new programmed value.

3.7

Fail safe mode

3.7.1

Temporary failures

SPSB081 enters fail-safe mode in case of:

•

Watchdog failure

•

V1 failure (V1 < VRTX for t > tV1FS)

•

Thermal shutdown TSD2

The fail-safe functionality is also available in V1_Standby mode. During V1_Standby mode the fail-safe mode is

entered in the following cases:

•

Watchdog failure (if watchdog still running due to IV1 > ICMP)

•

V1 failure (V1 < VRTX for t > tV1FS)

•

Thermal shutdown TSD2

In fail-safe mode, the device returns to a fail-safe state. The fail-safe condition is indicated to the system in the

global status byte. The conditions during the fail-safe mode are:

•

All outputs and V2 are turned off

•

All control registers are set to default values

•

Write operations to control registers are blocked until the fail-safe condition is cleared (see table below).

Only the following bits are not write-protected:

–

CR1 (0x01):

◦

TRIG

◦

CAN_ACT

–

CR2 (0x02):

◦

Timer settings (bits 8…13 and bits 16…21)

–

CR5 (0x05):

◦

OUT1_x (bits 0…2)

◦

OUT2_x (bits 4…6)

◦

OUT3_x (bits 8…10)

◦

OUT4_x (bits 12…14)

–

CR9 (0x09) to CR11 (0x0B)

◦

PWM frequency and duty cycles

–

Config register (0x3F)

◦

V2_0

◦

V2_1

•

LIN transmitter remains on

•

CAN FD transceiver remains on

•

Wake-up is enabled

•

Corresponding failure bits in status registers are set.

•

FS bit (bit 0 global status byte) is set

SPSB081

Fail safe mode

DS14048 - Rev 3

page 23/137

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