SPC563M60X datasheet(65/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Pinout and signal description

127

CAN_A_RX

CAN_C_RX

FlexCAN_A –

FlexCAN_C

FlexCAN receive

JCOMP

JTAG

Enables the JTAG TAP controller.

TCK

JTAG

Clock input for the on-chip test and debug logic.

TDI

JTAG

Serial test instruction and data input for the on-chip test and

debug logic.

TDO

JTAG

Serial test data output for the on-chip test logic.

TMS

JTAG

Controls test mode operations for the on-chip test and debug

logic.

EVTI

Nexus

EVTI is an input that is read on the negation of RESET to

enable or disable the Nexus Debug port. After reset, the EVTI

pin is used to initiate program synchronization messages or

generate a breakpoint.

EVTO

Nexus

Output that provides timing to a development tool for a single

watchpoint or breakpoint occurrence.

MCKO

Nexus

MCKO is a free running clock output to the development tools

which is used for timing of the MDO and MSEO signals.

MDO[3:0]

Nexus

Trace message output to development tools. This pin also

indicates the status of the crystal oscillator clock following a

power-on reset, when MDO[0] is driven high until the crystal

oscillator clock achieves stability and is then negated.

MSEO[1:0]

Nexus

Output pin—Indicates the start or end of the variable length

message on the MDO pins

BOOTCFG[1]

SIU – Configuration

The BOOTCFG1 pin is sampled during the assertion of the

RSTOUT signal, and the value is used to update the RSR and

the BAM boot mode

The following values are for BOOTCFG[0:1}:

0 Boot from internal Flash memory

1 FlexCAN/eSCI boot

WKPCFG

SIU – Configuration

The WKPCFG pin is applied at the assertion of the internal

reset signal (assertion of RSTOUT), and is sampled 4 clock

cycles before the negation of the RSTOUT pin.

The value is used to configure whether the eTPU and eMIOS

pins are connected to internal weak pull up or weak pull down

devices after reset. The value latched on the WKPCFG pin at

reset is stored in the Reset Status Register (RSR), and is

updated for all reset sources except the Debug Port Reset and

Software External Reset.

0: Weak pulldown applied to eTPU and eMIOS pins at reset

1: Weak pullup applied to eTPU and eMIOS pins at reset.

ETRIG[2:3]

SIU – eQADC Triggers

External signal eTRIGx triggers eQADC CFIFOx

IRQ[0:15]

SIU – External

Interrupts

The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select

IRQs.

Table 6. Signal details (continued)

Signal

Module or Function

Description

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