SPC563M60X datasheet(28/128 Pages) STMICROELECTRONICS

28 / 128 page

Overview

SPC563M64x, SPC563M60x

28/128

DocID14642 Rev 12



A new User Programmable Channel Mode has been added: the blocking, enabling,

service request and capture characteristics of this channel mode can be programmed

via microcode.



Microinstructions now provide an option to issue Interrupt and Data Transfer requests

selected by channel. They can also be requested simultaneously at the same

instruction.



Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the

entry point.



Channel digital filters can be bypassed.



The Timer Counter (TCR1), channel logic and digital filters (both channel and the

external timer clock input [TCRCLK]) now have an option to run at full system clock

speed or system clock / 2.



Channels support unordered transitions: transition 2 can now be detected before

transition 1. Related to this enhancement, the transition detection latches (TDL1 and

TDL2) can now be independently negated by microcode.



A new User Programmable Channel Mode has been added: the blocking, enabling,

service request and capture characteristics of this channel mode can be programmed

via microcode.



Microinstructions now provide an option to issue Interrupt and Data Transfer requests

selected by channel. They can also be requested simultaneously at the same

instruction.



Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the

entry point.



Channel digital filters can be bypassed.



32 channels, each channel is associated with one input and one output signal

–

Enhanced input digital filters on the input pins for improved noise immunity.

–

Identical, orthogonal channels: each channel can perform any time function. Each

time function can be assigned to more than one channel at a given time, so each

signal can have any functionality.

–

Each channel has an event mechanism which supports single and double action

functionality in various combinations. It includes two 24-bit capture registers, two

24-bit match registers, 24-bit greater-equal and equal-only comparators

–

Input and output signal states visible from the host



2 independent 24-bit time bases for channel synchronization:

–

First time base clocked by system clock with programmable prescale division from

2 to 512 (in steps of 2), or by output of second time base prescaler

–

Second time base counter can work as a continuous angle counter, enabling

angle based applications to match angle instead of time

–

Both time bases can be exported to the eMIOS timer module

–

Both time bases visible from the host



Event-triggered microengine:

–

Fixed-length instruction execution in two-system-clock microcycle

–

14 KB of code memory (SCM)

–

3 KB of parameter (data) RAM (SPRAM)

–

Parallel execution of data memory, ALU, channel control and flow control sub-

instructions in selected combinations

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