STA680 datasheet(26/48 Pages) STMICROELECTRONICS

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Power supply ramp-up phase

STA680

26/48

DS5877 Rev 13

Power supply ramp-up phase

The external power supply circuit on the board has to ensure that all the power supplies are

ramped up to their specified levels. The ramp up phase of each power domain should start

at the same time.

The RESET_N pin must be kept low from the beginning.

For normal applications, the TESTMODE pin (Factory test mode enable) must be connected

to ground.

4.1

Oscillator setting time

Once the power supply has reached the operating level, the internal voltage regulator gets

functional after TDC1V8 = 1ms (see Table 4) and starts supplying the 1.8 V voltage to internal

IPs such as PLLs and Crystal Oscillator.

The PLL is powered up but not yet functional since the internal logic keeps it in bypass

mode until a stable clock is available and STA680 has entered the secondary boot phase.

As shown in Figure 7, if an external crystal is connected to the internal oscillator this will

output a correct waveform after TOSC = 400 μs (seeTable 4).

Alternatively, if no crystal is used, a digital clock must be supplied according to the

instructions detailed in Section 3.1. In this case the Power On timing diagram is the same as

Figure 7 where OSC_OUT is substituted by the external supplied stable reference clock

(alternatively BB1_BCK or CLK_IN).

The RESET_N pin must be kept low for an additional TRST = 2 ms both when using a crystal

and when using an external reference clock.

As described in Section 3.1 the internal clock configuration is defined by the status of the

pins ADAT3, BLEND and DAC256X; this is latched on the rising edge of the RESET_N

signal.

The voltage of the three pins must be stable from at least TCFG = 0.1 μs before the rising

edge of the RESET_N signal.

4.2

Boot sequence

Once the RESET_N signal has been released and the power up sequence correctly

executed, the STA680 enters the boot procedure, which consists of two phases:

device setup

application authentication and download.

During the first phase, the STA680 executes the on-chip primary boot code contained in the

Boot ROM.

The primary boot synchronizes the internal cores, initializes the SPI and IIC interfaces and

automatically selects the secondary boot code source by looking for a pre-defined pattern

into UART1, ,Flash (SPI2), IIC1.

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