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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA680 데이터시트(PDF) 27 Page - STMicroelectronics |
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STA680 데이터시트(HTML) 27 Page - STMicroelectronics |
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27 / 48 page  DS5877 Rev 13 27/48 STA680 Power supply ramp-up phase 47 Once the source of the secondary boot code has been identified, the STA680 executes the following steps: 1. code authentication 2. SDRAM initialization 3. secondary boot code download to SDRAM. In order to decrease the boot time during the secondary phase, the STA680 performs the setup of the PLLs and sets the internal clock frequency to 28.224 MHz (see Figure 7). Subsequently it downloads and validates the application code either from the external Flash memory or from the host microcontroller. This ends the boot procedure. 4.3 Normal operation mode After the execution of the boot code, the device enters the normal operation mode by jumping to the main program loop. |
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