STA680 datasheet(36/48 Pages) STMICROELECTRONICS

36 / 48 page

Digital I/O and memory interfaces

STA680

36/48

DS5877 Rev 13

5.6.1

Host micro I2C interface (I2C1)

I2C1 is used to connect the STA680 to the host microcontroller to transmit commands,

diagnostic information, and data.

The I2C1 interface is a standard bi-directional I2C interface.

The I2C1 interface supports 7-bit addressing and 8-bit data. It can run in both standard

mode (serial clock frequency up to 100 kHz) and fast mode (up to 400 kHz). The I2C device

addresses are reported in Table 15.

An additional control line called IIC1_DA is provided as an extension of the I2C standard.

This line is used as a flag to show the host controller that data is available and it can be

polled by the host micro in either master or slave modes.

5.7

SDRAM interface

The SDRAM interface supports up to 32M x 16 SDRAM; both standard and mobile protocols

are accepted. For the relevant pin description see Table 16.

The minimum required SDRAM size for single channel application is 64 Mbit (a specific FW

is needed) while for a dual channel application at least 128 Mbit are needed.

Figure 13 shows the timing diagrams and waveform for the SDRAM interface.

Table 15. I2C1 interface device address

I2C1

Primary address

Secondary address

Read Address

00101111b (0x2F)

00101101b (0x2D)

Write Address

00101110b (0x2E)

00101100b (0x2C)

Table 16. SDRAM Interface pin description

Pin Name

Designation

Type

Drive

SDR_D[0:15]

SDRAM interface data bus

I/O

4 mA

SDR_A[0:12]

SDRAM interface address bus

4 mA

SDR_BA[0:1]

Bank address

4 mA

SDR_CAS_N

Active-low column address strobe

8 mA

SDR_RAS_N

Active-low row address strobe

8 mA

SDR_WE_N

Active-low write enable

8 mA

SDR_CS_N

Active-low chip select

8 mA

SDR_DQM0

low-byte data input/output mask

4 mA

SDR_DQM1

high-byte data input/output mask

4 mA

SDR_CKE

Clock enable

4 mA

SDR_CLK_RAM3V3

Clock to SDRAM for 3.3 V interface

8 mA

SDR_FEED_CLK

Feedback clock from SDRAM

8 mA

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