XIO2001IPNP datasheet(35/145 Pages) TI2

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Figure 8-7. Continuing a Locked Sequence

Because PCI Express does not have a unique locked-memory write request packet, all PCI Express memory

write requests that are received while the bridge is locked are considered part of the locked sequence and are

transmitted to PCI as locked-memory write transactions.

The bridge terminates the locked sequence when an unlock message is received from PCI Express and all

previous locked transactions have been completed.

CLK

FRAME

LOCK

IRDY

Figure 8-8. Terminating a Locked Sequence

In the erroneous case that a normal downstream memory read request is received during a locked sequence,

the bridge responds with an unsupported request completion status. Note that this condition must never occur,

because the PCI Express Specification requires the root complex to block normal memory read requests at the

source. All locked sequences that end successfully or with an error condition must be immediately followed by

an unlock message. This unlock message is required to return the bridge to a known unlocked state.

8.3.8 Two-Wire Serial-Bus Interface

The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific

of the GPIO terminals (3 and 4). If the serial bus interface is enabled, then the GPIO3 and GPIO4 terminals are

disabled. If the serial bus interface is disabled, then the GPIO terminals operate as described in Section 8.3.11.

8.3.8.1 Serial-Bus Interface Implementation

To enable the serial-bus interface, a pullup resistor must be implemented on the SCL signal. At the rising edge of

PERST or GRST, whichever occurs later in time, the SCL terminal is checked for a pullup resistor. If one is

detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 8.4.59) is set.

Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external

EEPROM is required, then the serial-bus interface is permanently disabled by attaching a pulldown resistor to

the SCL signal.

The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA).

The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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