XIO2001IPNP datasheet(90/145 Pages) TI2

90 / 145 page

Table 8-60. Cache Timer Transfer Limit Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:0(1)

CACHE_TMR_XFR

_LIMIT

Number of PCI cycle starts that have to occur without a read hit on the completion data

buffer, before the cache data can be discarded.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.4.78 Cache Timer Lower Limit Register

Minimum number of clock cycles that must have passed without a read hit on the completion data buffer before

the "cache miss limit" check can be triggered. See Table 8-61 for a complete description of the register contents.

PCI register offset:

ECh

Read/Clear

Default value:

007Fh

BIT NUMBER

RESET STATE

Table 8-61. Cache Timer Lower Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

11:0(1)

CACHE_TIMER

_LOWER_LIMIT

Minimum number of clock cycles that must have passed without a read hit on the

completion data buffer before the "cache miss limit" check can be triggered.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.4.79 Cache Timer Upper Limit Register

Discard cached data after this number of clock cycles have passed without a read hit on the completion data

buffer. See Table 8-62 for a complete description of the register contents.

PCI register offset:

EEh

Read/Clear

Default value:

01C0h

BIT NUMBER

RESET STATE

Table 8-62. Cache Timer Upper Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

11:0(1)

CACHE_TIMER

_UPPER_LIMIT

Discard cached data after this number of clock cycles have passed without a read hit on

the completion data buffer.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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