XIO2001IPNP datasheet(98/145 Pages) TI2

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8.5.10 Secondary Uncorrectable Error Status Register

The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur.

Software may only clear these bits by writing a 1b to the desired location. See Table 8-70 for a complete

description of the register contents.

PCI Express extended register offset:

12Ch

Read-only, Read/Clear

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 8-70. Secondary Uncorrectable Error Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns 000 0000 0000 0000 0000b when read.

INTERNAL_ERROR

Internal bridge error. This error bit is associated with a PCI-X error and returns 0b when

read.

12(1)

SERR_DETECT

RCU

SERR assertion detected. This bit is asserted when the bridge detects the assertion of

SERR on the secondary bus.

11(1)

PERR_DETECT

RCU

PERR assertion detected. This bit is asserted when the bridge detects the assertion of

PERR on the secondary bus.

10(1)

DISCARD_TIMER

RCU

Delayed transaction discard timer expired. This bit is asserted when the discard timer

expires for a pending delayed transaction that was initiated on the secondary bus.

9(1)

UNCOR_ADDR

RCU

Uncorrectable address error. This bit is asserted when the bridge detects a parity error

during the address phase of an upstream transaction.

UNCOR_ATTRIB

Uncorrectable attribute error. This error bit is associated with a PCI-X error and returns 0b

when read.

7(1)

UNCOR_DATA

RCU

Uncorrectable data error. This bit is asserted when the bridge detects a parity error during a

data phase of an upstream write transaction, or when the bridge detects the assertion of

PERR when forwarding read completion data to a PCI device.

UNCOR_SPLTMSG

Uncorrectable split completion message data error. This error bit is associated with a PCI-X

error and returns 0b when read.

UNXPC_SPLTCMP

Unexpected split completion error. This error bit is associated with a PCI-X error and

returns 0b when read.

RSVD

Reserved. Returns 0b when read.

3(1)

MASTER_ABORT

RCU

Received master abort. This bit is asserted when the bridge receives a master abort on the

PCI interface.

2(1)

TARGET_ABORT

RCU

Received target abort. This bit is asserted when the bridge receives a target abort on the

PCI interface.

MABRT_SPLIT

Master abort on split completion. This error bit is associated with a PCI-X error and returns

0b when read.

TABRT_SPLIT

Target abort on split completion status. This error bit is associated with a PCI-X error and

returns 0b when read.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.5.11 Secondary Uncorrectable Error Severity

The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or

ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is

cleared, the corresponding error condition is identified as nonfatal. See Table 8-71 for a complete description of

the register contents.

PCI Express extended register offset:

134h

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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