XIO2001IPNP datasheet(43/145 Pages) TI2

43 / 145 page

Table 8-11. Classic PCI Configuration Register Map (continued)

OFFSET

Device Status 2

Device Control 2

098h

Link Capabilities 2

09Ch

Link Status 2

Link Control 2

0A0h

Slot Capabilities 2

0A4h

Slot Status 2

Slot Control 2

0A8h

Reserved

0ACh

Serial-bus control and status(1)

Serial-bus slave address(1)

Serial-bus word address(1)

Serial-bus data(1)

0B0h

GPIO data(1)

GPIO control(1)

0B4h

Reserved

0B8h–0BCh

TL Control and diagnostic register 0(1)

0C0h

DLL Control and diagnostic register 1(1)

0C4h

PHY Control and diagnostic register 2(1)

0C8h

Reserved

0CCh

Subsystem access(1)

0D0h

General control(1)

0D4h

Reserved

Clock run status(1)

Clock mask

Clock control

0D8h

Reserved

Arbiter time-out status

Arbiter request mask(1)

Arbiter control(1)

0DCh

Serial IRQ edge control(1)

Reserved

Serial IRQ mode control(1)

0E0h

Reserved

Serial IRQ status

0E4h

Cache Timer Transfer Limit

PFA Request Limit

0E8h

Cache Timer Upper Limit

Cache Timer Lower Limit

0ECh

Reserved

0F0h–0FCh

(1)

One or more bits in this register are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

Registers highlighted in gray are reserved or not implemented.

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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