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XIO2001IPNP 데이터시트(PDF) 76 Page - Texas Instruments

부품명 XIO2001IPNP
상세설명  XIO2001 PCI Express to PCI Bus Translation Bridge
PDF  145 Pages
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XIO2001IPNP 데이터시트(HTML) 76 Page - Texas Instruments

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BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 8-47. Control and Diagnostic Register 2 Description
BIT
FIELD NAME ACCESS
DESCRIPTION
31:24(1) N_FTS_
ASYNC_CLK
RW
N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see Section
8.4.54) is clear, the value in this field is the number of FTS that are sent on a transition from L0s to L0.
This field shall default to 32h.
23:16(1) N_FTS_
COMMON_
CLK
RW
N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section
8.4.54) is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0.
This field defaults to 14h.
15:13
PHY_REV
R
PHY revision number
12:8(1) LINK_NUM
RW
Link number
7(1)
EN_L2_PWR_
SAVE
RW
Enable L2 Power Savings
0=
1=
Power savings not enabled when in L2
Power savings enabled when in L2.
6
RSVD
R
Reserved. Returns 0b when read.
5(1)
BAR0_EN
RW
BAR 0 Enable.
0 =
1 =
BAR at offset 10h is disabled (default)
BAR at offset 10h is enabled
4:0(1)
RSVD
RW
Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00000b.
(1)
These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.
XIO2001
SCPS212J – MAY 2009 – REVISED JANUARY 2021
www.ti.com
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