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ADAR4002ACPZ-R7 데이터시트(PDF) 44 Page - Analog Devices

부품명 ADAR4002ACPZ-R7
상세설명  0.5 GHz to 19 GHz, 1-Channel, Bidirectional True Time Delay Unit
PDF  66 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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ADAR4002ACPZ-R7 데이터시트(HTML) 44 Page - Analog Devices

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Data Sheet
ADAR4002
THEORY OF OPERATION
analog.com
Rev. A | 44 of 66
zero padding bits can be eliminated from the SPI transaction to
reduce data transfer time.
Note that any changes in these streamwrite registers also change
the corresponding data in the regular TDU and DSA data registers
(Register 0x20 through Register 0x5F), and vice versa. Also note
that the data is arranged in an ascending address block write. Bit
5 and Bit 2 must be asserted high in Register 0x000 for address
ascension.
Register 0xF0 and Register 0xF1
The current time delay and DSA values being applied to the
TDU and DSA blocks can be read back from Registers 0xF0 and
Register 0xF1.



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