ST7FLCD1 datasheet(75/95 Pages) STMICROELECTRONICS

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ST7FLCD1

Watchdog Timer (WDG)

12.1

Introduction

The Watchdog Timer is used to detect the occurrence of a software fault, usually generated by

external interference or by unforeseen logical conditions, which causes the application program to

abandon its normal sequence. The Watchdog circuit generates an MCU reset when the

programmed time period expires, unless the program refreshes the counter’s contents before the

T6 bit is cleared. In addition, a second counter prevents the Watchdog register from being updated

at intervals that are too close.

12.2

Main Features

● Programmable timer (64 increments of 50000 CPU cycles)

● Programmable reset

● Reset (if watchdog enabled) when the T6 bit reaches zero

● Reset (if watchdog enabled) on HALT instruction

● Lock-up Counter for preventing short time refreshes

12.3

Main Watchdog Counter

The counter value stored in the CR register (bits T[6:0]), is decremented every 50000 clock cycles,

and the length of the time out period can be programmed by the user in 64 increments.

If the watchdog is enabled (bit WDGA is set) and when the 7-bit timer (bits T[6:0]) rolls over from

40h to 3Fh (T6 is cleared), it initiates a reset cycle pulling low the reset pin for typically 500 ns:

● The WDGA bit is set (watchdog enabled)

● Bit T6 is set to prevent generating an immediate reset

● Bits T[5:0] contain the number of increments which represents the time delay before the

watchdog produces a reset.

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

Figure 40: Watchdog Block Diagram

Reset

WDGA

7-bit Downcounter

fCPU

Clock Divider

Watchdog Control Register (CR)

÷50000

Lock-up Counter

(256 fCPU)

Write

Access

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