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ST7FLCD1 데이터시트(PDF) 91 Page - STMicroelectronics

부품명 ST7FLCD1
상세설명  8-bit MCU for LCD Monitors with 60 KBytes Flash,2 KBytes RAM, 2 DDC Ports and Infrared Controller
PDF  95 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST7FLCD1 데이터시트(HTML) 91 Page - STMicroelectronics

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ST7FLCD1
Electrical Characteristics
17.7
I2C/DDC Bus Electrical Specifications
Note:
na = not applicable
Cb = capacitance of one bus in pF
17.8
I2C/DDC Bus Timings
Note:1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL.
Symbol
Parameter
Standard mode
Fast mode
Unit
Min.
Max.
Min.
Max.
VHYS
Hysteresis of Schmitt trigger inputs
Fixed input levels
VDD-related input levels
na
na
na
na
0.2
0.05 VDD
V
TSP
Pulse width of spikes which must be suppressed
by the input filter
na
na
0 ns
50 ns
ns
TOF
Output fall time from VIH min to VIL max with a
bus capacitance from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
na
250
na
20+0.1Cb
20+0.1Cb
250
250
ns
I
Input current each I/O pin with an input voltage
between 0.4V and 0.9 VDD max
- 10
10
-10
10
µA
C
Capacitance for each I/O pin
10
10
pF
Symbol
Parameter
Standard I2C
Fast I2C
Unit
Min.
Max.
Min.
Max.
tBUF
Bus free time between a STOP and START
condition
4.7
1.3
ms
tHD:STA
Hold time START condition. After this period, the
first clock pulse is generated
4.0
0.6
µs
tLOW
LOW period of the SCL clock
4.7
1.3
µs
tHIGH
HIGH period of the SCL clock
4.0
0.6
µs
tSU:STA
Set-up time for a repeated START condition
4.7
0.6
µs
tHD:DAT
Data hold time
0 (1)
0 (1)
0.9(2)
ns
tSU:DAT
Data set-up time
250
100
ns
tR
Rise time of both SDA and SCL signals
1000
20+0.1Cb
300
ns
tF
Fall time of both SDA and SCL signals
300
20+0.1Cb
300
ns
tSU:STO
Set-up time for STOP condition
4.0
0.6
ns
Cb
Capacitive load for each bus line
400
400
pF



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