ST7FLCD1 datasheet(82/95 Pages) STMICROELECTRONICS

82 / 95 page

8-bit Timer with External Trigger (TIMB)

ST7FLCD1

82/95

Bit 4 = OVFE Timer Overflow Interrupt Enable

This bit is set and cleared by software.

Interrupt disabled

Interrupt enabled

Bit 3 = TAR Timer Auto Reload

This bit is set and cleared by software.

One-shot mode. The counter restarts after writing to the TIMCPRB register.

Auto reload mode. The counter is reloaded automatically from the TIMCPRB register when 00h

is reached.

Bit 2 = EXT External Trigger

This bit is set and cleared by software.

Internal. The downcounter restarts after writing to the TIMCPRB register or after an auto-reload

if the TAR bit is set

External. The downcounter is preloaded with the TIMCPRB register but the countdown starts

only when the external signal is detected, not by writng to the TIMCPRB register.

Bit 1 = EDG External Signal Edge

This bit is set and cleared by software.

A rising edge signal starts the count-down.

A falling edge signal starts the count-down

Bit 0 = EEF External Event Flag

This bit is set and cleared by hardware when an external event occurs.

This bit is cleared when the counter reaches “00h” in External mode or when the value of the EXT

bit is changed by software.

In Internal mode, this bit is set when the selected edge is detected (the EDG bit) but it is never

cleared by itself. It may then be used as a simple edge detector.

TIMER B COUNTER PRELOAD REGISTER (TIMCPRB)

Read/Write

Reset value: (01h)

Bits [7:0] = PR[7:0] Counter Preload Data

This bit is set and cleared by software.

Bits hold the reload value which is loaded in the counter either immediately (EXT = 0) or when the

external signal is detected (EXT = 1).

Note:

The N number loaded in TIMCPRB register corresponds to a time of (N + 1) x Period timer.

The "00" value is prohibited.

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

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