M58LR128KB855 datasheet(16/110 Pages) NUMONYX

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Bus operations

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

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Bus operations

There are six standard bus operations that control the device. These are bus read, bus

write, address latch, output disable, standby and reset. See Table 4: Bus operations for a

summary.

Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus write operations.

3.1

Bus read

Bus read operations are used to output the contents of the memory array, the electronic

signature, the Status Register and the Common Flash interface. Both Chip Enable and

Output Enable must be at VIL to perform a read operation. The Chip Enable input should be

used to enable the device, and Output Enable should be used to gate data onto the output.

The data read depends on the previous command written to the memory (see command

interface section). See Figures 9, 10 and 11 read AC waveforms, and Tables 24 and 25 read

AC characteristics for details of when the output becomes valid.

3.2

Bus write

Bus write operations write commands to the memory or latch input data to be programmed.

A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output

Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the

write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable

must be tied to VIH during the bus write operation.

See Figures 15 and 16, write AC waveforms, and Tables 26 and 27, write AC characteristics

for details of the timing requirements.

3.3

Address Latch

Address latch operations input valid addresses. Both Chip enable and Latch Enable must be

at VIL during address latch operations. The addresses are latched on the rising edge of

Latch Enable.

3.4

Output disable

The outputs are high impedance when the Output Enable is at VIH.

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