TMS320DM647_0804 datasheet(66/182 Pages) TI

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6.4.3

PLL1 Stabilization, Lock, and Reset Times

6.4.4

PLL1 Controller Input and Output Clock Electrical Data/Timing

CLKIN

6.4.5

PLL1 Controller Register Description(s)

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is

changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration

has completed.

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after device power-up. The PLL should not be operated until this stabilization time has

finished.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1) for the

PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time

value, see Table 6-7.

Table 6-7. PLL1 Stabilization, Lock, and Reset Times

MIN

TYP

MAX

UNIT

PLL stabilization time

150

µs

PLL lock time

2000

× C(1)

µs

PLL reset time

128

× C(1)

µs

(1)

C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

Table 6-8. Timing Requirements for CLKIN1 (1)(2)(3) (see Figure 6-6)

720

900

PLL MODES

NO.

UNIT

x1 (Bypass), x15, x20,

x25, x30, x32

MIN

MAX

tc(CLKIN1)

Cycle time, CLKIN1

tw(CLKIN1H)

Pulse duration, CLKIN1 high

0.4C

tw(CLKIN1L)

Pulse duration, CLKIN1 low

0.4C

tt(CLKIN1)

Transition time, CLKIN1

1.2

tJ(CLKIN1)

Period jitter, (peak-to-peak), CLKIN1

100

(1)

The reference points for the rise and fall transitions are measured at 3.3-V VIL MAX and VIH MIN.

(2)

C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

(3)

The PLL1 multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32) further limit the MIN and MAX values for tc(CLKIN1). For more

detailed information on these limitations, see Section 6.3.5, Power and Clock Domains.

Figure 6-6. CLKIN1 Timing

A summary of the PLL1 controller registers is shown in Table 6-9.

Peripheral Information and Electrical Specifications

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