TMS320DM647_0804 datasheet(76/182 Pages) TI

76 / 182 page

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

Table 6-14. EDMA Channel Controller Registers (continued)

HEX ADDRESS

ACRONYM

0x02A0 2000- 0x02A0 2097

Shadow Region 0 Channel Registers

0x02A0 2098 - 0x02A0 21FF

Reserved

0x02A0 2200 - 0x02A0 2297

Shadow Region 1 Channel Registers

0x02A0 2298 - 0x02A0 23FF

Reserved

0x02A0 2400 - 0x02A0 2497

Shadow Region 2 Channel Registers

0x02A0 2498 - 0x02A0 25FF

Reserved

0x02A0 2600 - 0x02A0 2697

Shadow Region 3 Channel Registers

0x02A0 2698 - 0x02A0 27FF

Reserved

0x02A0 2800 - 0x02A0 2897

Shadow Region 4 Channel Registers

0x02A0 2898 - 0x02A0 29FF

Reserved

0x02A0 2A00 - 0x02A0 2A97

Shadow Region 5 Channel Registers

0x02A0 2A98 - 0x02A0 2BFF

Reserved

0x02A0 2C00 - 0x02A0 2C97

Shadow Region 6 Channel Registers

0x02A0 2C98 - 0x02A0 2DFF

Reserved

0x02A0 2E00 - 0x02A0 2E97

Shadow Region 7 Channel Registers

0x02A0 2E98 - 0x02A0 2FFF

Reserved

Table 6-15 shows an abbreviation of the set of registers that make up the parameter set for each of 128

EDMA events. Each of the parameter register sets consist of eight 32-bit word entries. Table 6-16 shows

the parameter set entry registers with relative memory address locations within each of the parameter

sets.

Peripheral Information and Electrical Specifications

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