| 전자부품 데이터시트 검색엔진 |
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S2-LPS 데이터시트(PDF) 19 Page - STMicroelectronics |
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S2-LPS 데이터시트(HTML) 19 Page - STMicroelectronics |
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19 / 73 page ![]() The S2-LPS PM can be configured by SPI (BYPASS_LDO field in PM_CONFIG [1] register) in two main modes: 1. High performance mode (HPM) 2. Low power mode (LPM) In HPM all available LDOs supplied from SMPS are used, to get the best possible isolation and minimum low-frequency noise level and SMPS ripple. SMPS must be set to 1.4 V at least. In LPM the LDOs connected to the SMPS are by-passed and SMPS must be configured to provide 1.2 V output level to increase the regulation efficiency but with reduced isolation and higher low-frequency noise and SMPS ripple. The load inductor of the SMPS has to have the following characteristics: • A typical 10 µH nominal value +/-10% • A rated current of 100 mA minimum • A DC resistance as low as possible (to guarantee maximum efficiency of the SMPS block), around 1 Ohm is a typically good value, but the lower the better 4.2 Power-On-Reset The Power-On-Reset (POR) circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. Power-on-reset senses VBAT voltage. The S2-LPS provides an automatic POR circuit, which generates an internal RESETN (active low) level for a time TRESET, after the VBAT reaches the reset release voltage threshold VRRT, as shown in Figure 6. Power-On-Reset timing and limits. The same reset pulse is generated after a step-down on the input pin SDN (VDD>VRRT). This signal is available on the GPIO0 pin. Figure 6. Power-On-Reset timing and limits The parameters VRRT and TRESET are fixed by design in order to guarantee a reliable reset procedure of the state machine. In addition, all the registers are initialized to their default values. A software command SRES is also available, it generates an internal but partial resetting of the S2-LPS. Table 29. POR parameters Parameter Comment Min. Typ. Max. Unit Reset start-up threshold voltage 0.5 V Hold pulse width (Thold, figure below) For SDN to be effective 1 µs S2-LPS Power-On-Reset DS13831 - Rev 1 page 19/73 |
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