S2-LPS datasheet(37/73 Pages) STMICROELECTRONICS

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Initial state

Final state

Response time [µs]

READY

STANDBY/ SLEEP

READY

LOCK with no VCO calibration

READY

LOCK with VCO calibration

RX/TX

READY

STANDBY/SLEEP

READY

100

LOCK

RX/TX

Note:

The transition time enables the S2-LPS for frequency hopping operation due to its reduced response time and

very quick programming synthesizer. The response time depends on frequency of the clock in digital domain,

from 24 MHz to 26 MHz.

Note:

The first bit of preramble is sent after TX state is reached, if PA ramping is not enabled. If PA ramping is

enabled, the first bit is sent after tramp (see Section 4.4.6.1 PA configuration).

5.3

Sleep states

S2-LPS provides 2 SLEEP states:

•

SLEEP without FIFO retention (SLEEP_A): in this low power state, the device keeps all the register values

but not the TX and RX FIFOs. This is the device default SLEEP state.

•

SLEEP with FIFO retention (SLEEP_B): in this low power state, the device keeps the content of the registers

and the two FIFOs.

The responsibility of the SLEEP type to be used is demanded to the user. To select the SLEEP mode, the bit

SLEEP_MODE_SEL (register 0x79) can be used. If this bit is set to 0, SLEEP_A is used each time the device

enters SLEEP (by SPI command, LDC flow in non-persistent mode). If it is 1, SLEEP_B is used instead.

S2-LPS

Sleep states

DS13831 - Rev 1

page 37/73

S2-LPS 데이터시트(PDF) 37 Page - STMicroelectronics