RIVA128 datasheet(64/77 Pages) STMICROELECTRONICS

64 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

64/77

Byte offsets 0x07 - 0x04

Device Status Register (0x07 - 0x06)

Command Register (0x05 - 0x04)

0x07

0x06

0x05

0x04

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits

Function

R W I

Reserved

R - 0

SERR_SIGNALLED is set whenever the RIVA 128 asserts SERR#.

R W 0

RECEIVED_MASTER indicates that a master device's transaction (except for

Special Cycle) was terminated with a master-abort. This bit is clearable (=1).

0=No abort

1=Master aborted

R W 0

RECEIVED_TARGET indicates that a master device's transaction was termi-

nated with a target-abort. This bit is clearable (=1).

0=No abort

1=Master received target aborted

R W 0

Reserved

R - 0

26:25

The DEVSEL_TIMING bits indicate the timing of DEVSEL#. These bits indi-

cate the slowest time that the RIVA 128 asserts DEVSEL# for any bus com-

mand except Configuration Read and Configuration Write. The RIVA 128

responds with medium DEVSEL# for VGA, memory and I/O accesses. For

accesses to the 16MByte memory ranges described by the BARs, the chip

responds with fast decode (no wait states).

00=fast

01=medium

R - 1

24:22

Reserved

R - 0

66MHZ indicates that the RIVA 128 is capable of 66MHz operation. This bit

reflects the latched state of the 66MHz/33MHz strap option.

R - 1

CAP_LIST indicates that there is a linked list of registers containing informa-

tion about new capabilities not available within the original PCI configuration

structure. This bit indicates that the (byte) Capability Pointer Register located

at 0x34 points to the start of this linked list.

R - 1

19:16

Reserved

R - 0

Bits

Function

R W I

15:9

Reserved

R - 0

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