RIVA128 datasheet(71/77 Pages) STMICROELECTRONICS

71 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

71/77

Byte offsets 0x33 - 0x30

Expansion ROM Base Address Register (0x33 - 0x30)

0x33

0x32

0x31

0x30

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits

Function

R W I

31:22

The ROM_BASE_ADDR bits contain the base address of the Expansion

ROM. The bits correspond to the upper bits of the Expansion ROM base

address. This decode permits the PCI boot manager to place the expansion

ROM on a 4MByte boundary. RIVA 128 currently maps a 64KByte BIOS into

the bottom of this 4MByte range. Typically the first 32K of this ROM contains

the VGA BIOS code as well as the PCI BIOS Expansion ROM Header and

Data Structure.

R W X

21:11

ROM_BASE_RESERVED contain the lower bits of the base address of the

Expansion ROM. These bits are hardwired to 0, forcing a 4MByte boundary.

R - 0

10:1

Reserved

R - 0

The ROM_DECODE bit indicates whether or not the RIVA 128 accepts

accesses to its expansion ROM. When the bit is set, address decoding is

enabled using the parameters in the other part of the base register. The

MEMORY_SPACE bit (PCI Configuration Register 0x04, page 64) has prece-

dence over the ROM_DECODE bit. RIVA 128 will respond to accesses to its

expansion

ROM

only

both

the

MEMORY_SPACE

bit

and

the

ROM_DECODE bit are set to 1.

0=Expansion ROM address space is disabled

1=Expansion ROM address decoding is enabled

R W 0

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