RIVA128 datasheet(32/77 Pages) STMICROELECTRONICS

32 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

32/77

Figure 26.

SGRAM random read accesses within a page, read latency of two1

NOTE

Covers either successive reads to the active row in a given bank, or to the active rows in different banks. DQMs are all

active (LOW).

Figure 27.

SGRAM random read accesses within a page, read latency of three1

NOTE

Covers either successive reads to the active row in a given bank, or to the active rows in different banks. FBDQM is all

active (LOW).

tCL

CLK low time

3.5

4.5

tAS

Address setup time

tAH

Address hold time

tDS

Write data setup time

tDH

Write data hold time

tOH

Read data hold time

tAC

Read data access time

tLZ

Data out low impedance time

Symbol

Parameter

Min.

Max.

Unit

Notes

-10

-12

-10

-12

read

data n

data a

read

nop

bank, col n bank, col a bank, col x bank, col m

data x

data m

FBCLKx

Command

FBA[9:0]

FBD[63:0]

read

data n

read

nop

bank, col n bank, col a bank, col x bank, col m

data a

data x

data m

nop

FBCLKx

Command

FBA[9:0]

FBD[63:0]

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